1. Field of the Invention
The present invention relates to data processing systems and, more particularly, to devices for performing data transfer in a computer system.
2. Description of Related Art
In conventional computer systems, data is processed by transferring and decoding instructions, such as from software programs, that define operations to be performed. Within these instructions are data transfer requests for transferring data throughout the computer system. These computer systems typically have extensive memory banks that take on a variety of characteristics. In particular, synchronous DRAM ("syncDRAM") memories are a modern advancement that provides DRAM capability where the outputs are referenced to the rising edge of the system clock pulse. Furthermore, when a read operation is performed, more than one word is loaded into a high speed shift register where these words are shifted out, one word per clock cycle. These multi-word transfers are called "bursts". As a result, a memory system built out of syncDRAMs has a peak (ideal) bandwidth equal to the system's clock frequency multiplied by the number of data lines in the system's bus. Therefore, the memory bandwidth is directly proportional to the clock frequency.
Modern syncDRAMs can deliver a burst of information of four to eight cycles of data, with the address word appearing first followed by the remainder of the block. This allows for a large amount of data to be transferred at the same rate as the system clock. Each burst of data is transferred in response to a primary request from a microprocessor, the primary request having a corresponding address that is latched in the syncDRAM with the command sent by the microprocessor. The primary request could also originate from the PCI master controller or any other peripheral controller sitting off of a PCI bridge.
In a typical data request from a syncDRAM, the host interface which interprets the system bus, or host bus, of the computer system sends a request out for data in response to a command from a microprocessor. The receiving unit in the system indicates its readiness to do the cycle requested by the host interface by asserting an ARM signal back to the system. The syncDRAM interface will begin to drive a cycle to SyncDRAM on the rising edge of the system clock in which both the ARM signal and the request signal from the host interface are sampled active together. A data transfer controller (sometimes referred to in the art as the B-unit) having buffer memory capable of storing addresses controls the transfer of data between the syncDRAM memory and the PCI bus. The data transfer controller provides an interface between the host interface, the syncDRAM memory and the peripheral component interface (PCI) of the system. With the added complexity in modern systems of additional data transfer request sources (other than the CPU) and maintaining cache coherency, the B-unit is crucial in modern computer systems. The data transfer controller provides for interface among these components, keeps track of what data is in the correct buffers and determines whether a certain cycle can start or if an ongoing cycle needs to be completed. The buffers in the data transfer controller store addresses and controls what cycles will occur and when.
The data transfer controller signals the readiness of the controller to allow the cycle by initiating an ARM signal or BHarm which indicates the readiness of the data transfer controller to accept the cycle requested by the host interface. This indicates that the data transfer controller is either idle or simply has the capacity to accept the cycle. After the transfer controller asserts BHarm, the receiving unit then can begin receiving data.
After the data has been requested and sent, the syncDRAM is then ready to latch another address in response to a data transfer request and begin a new cycle. From the time when the data is finished being delivered until a number of clocks corresponding to the CAS latency of the syncDRAM after the next request and address are received by the syncDRAM unit, a lag time occurs where no data is being transferred. Due to the CAS latency, the syncDRAM could receive a request on the clock after the last data was delivered and the result would still be a period of time equal to the CAS latency where no data is transferred. It would be useful during this time to continue transferring data from the syncDRAM unit. As will be seen, the present invention makes use of this time to transfer data from the syncDRAM unit in a simple, elegant manner.